The present invention relates generally to the fabrication of interconnect structures on a semiconductor device. More specifically, this invention pertains a dual damascene process used in the fabrication of interconnect structures and to interconnect structures incorporating low-k dielectric materials.
Several different dual damascene processes may be utilized in the fabrication of interconnect structures. One such process is the full via-first (“FVF”), which is illustrated in FIGS. 1 through 4. As shown in FIG. 1, a structure 10 prior to etching may have an interconnect layer 11 in which there is formed a metal interconnect feature 8. Overlaying layer 11 and feature 8 is a barrier layer 14. Over barrier layer 14 are two dielectric layers 12 and 13 separated by an intermediate etch stop layer 15. A patterned photoresist (“PR”) layer 16 is deposited over top dielectric layer 13.
A via feature is patterned in the photoresist layer 16 of a device or structure 10 using photolithography. As shown in FIG. 2, a via 17 is etched through the dielectric layers 13 and 12, and the etch stop layer 15, to the barrier layer 14. The photoresist layer 16 is then stripped from the semiconductor device and replaced with a new or fresh photoresist layer (not shown). A trench feature is patterned in the fresh photoresist layer. As shown in FIG. 3, a trench 18 is etched through the dielectric layer 13 to the etch stop layer 15. The fresh photoresist layer is then stripped. The etch stop layer 15 and the insulative barrier layer 14, exposed in the via 17, are then selectively etched. A thin copper barrier (not shown) together with a copper film 19 is then deposited in the trench 18 and via 17. The semiconductor device is planarized using chemical mechanical planarization to form the interconnect structure shown in FIG. 4.
As described above, after the via 17 is etched through the dielectric layers 12 and 13, a fresh photoresist material is deposited on the device 10, filling the via 17. A self-planarizing antireflection coating/photoresist, or ARC/photoresist, is used to provide a planar surface for sufficient focusing of the photolithographic instrument. Some drawbacks from the use of ARC/photoresist include the potential for micro-trench formation and the extension of the overall etch time required to remove the ARC in the via, with no guarantee that the via will be completely cleared. These problems can lead to reduced yield and less reliable devices.
Another problem exists in the interaction of the ARC/photoresist with the amine impurities in “low-k dielectric materials.” Dielectric materials having lower dielectric constants are known as low-k dielectric materials and have become increasingly popular in the fabrication of interconnect structures of semiconductor devices. The low-k dielectric materials typically have dielectric constants up to about 3.0. However, low-k dielectric materials are chemically reactive with photoresist materials or have impurities that react with the photoresist materials when the latter comes into contact with the low-k dielectric materials.
Reactions between the low-k dielectric materials and the photoresist materials are more severe during the trench formation where, apart from a surface interaction, there is also interaction within the via. This reaction between the photoresist material and the low-k dielectric material then blocks the trench patterning and prevents fabrication of interconnect structures using the traditional FVF dual damascene process.
These drawbacks have led to the use of alternative dual damascene processes that incorporate the use of a mask layer (also referred to as a “hard mask layer”) deposited over the low-k dielectric materials. A mask layer as used herein is a layer that includes a film, or composite films, that overlay a dielectric material in an interconnect structure, and serves as a barrier layer between a photoresist layer and a dielectric material. A mask layer may also be referred to as a hard mask layer or photoresist mask, which terms may be used interchangeably in this disclosure. The mask layer protects specific regions of the dielectric materials during the etching process.
The hard mask layers known in the prior art typically include two layers of different property films. The two mask films may include a first mask film usually consisting of SiC or Si3N4 and a second mask film consisting of silicon dioxide (SiO2). The two hard mask films prevent the photoresist materials from coming into contact with the low-k dielectric material during via and trench photolithography and etching. In addition, the first mask film, SiC or Si3N4, protects the low-k dielectric films from chemical mechanical polishing. It also serves as an insulator or diffusion barrier for the metal film to be deposited in a trench and via where its function is to prevent surface current or metallic ion leaks from the conductive metal deposited in the trench. The second hard mask film serves as a sacrificial layer where the trench or via is initially etched and is eliminated after the completion of all processes. It also helps protect the underlying dielectric layers when the via or trench pattern thereon is transferred to the underlying dielectric layers.
Dual damascene processes incorporating a mask layer are the partial-trench-first in a two layer hard mask (also referred to as the “PTF-2LM”), and the partial-via-first in two layer hard mask (also referred to as the “PVF-2LM”). A PTF-2LM dual damascene process is illustrated in FIGS. 5–8. The semiconductor device 20 shown in FIG. 5 includes a dielectric material comprising a via dielectric layer 22 and a trench dielectric layer 21 deposited over an underlying interconnect layer 23 having a conductive line 24. An insulative barrier layer 25 is disposed between the metal layer 23 and the via dielectric layer 22. An etch stop layer 26 is disposed between the via dielectric layer 22 and the trench dielectric layer 21. A mask layer 27, having a first mask film 27A and second mask film 27B, overlays the dielectric material. A photoreisist layer 28 has been deposited on the mask layer to pattern the trench feature.
With respect to FIG. 6, a site for the trench feature is first patterned in the photoresist layer 28, and then etched through the second mask film 27B to the first mask film 27A. The photoresist layer 28 is then removed, and replaced with a fresh photoresist layer 28A filling the trench 30. With respect to FIG. 7, a via 29 feature is patterned in the fresh photoresist layer 28A and etched through the dielectric layers 21, and 22 and to the insulative barrier layer 25. The fresh photoresist layer 28 is then stripped.
As shown in FIG. 8, the feature for the trench 30, which was patterned and etched in the mask layer 27, is then etched through the trench dielectric layer 21 to the etch stop layer 26. Since there is no photoresist material protection, an etch chemistry is chosen such that when the trench dielectric layer 21 is being etched, the first mask film of the mask layer is not etched. In a separate etching procedure, the etch stop layer 26 within the trench 30 and the barrier insulative layer 25, within the via 29, are selectively etched (not shown) so the via 29 may connect an underlying conductive line 24 to a conductive line formed in the trench 30.
The via 29 connects the conductive line 24 to the line formed in the trench 30. In order to achieve an optimum product yield and reliability, the via and trench features must align satisfactorily. In the above described PTF-2LHM dual damascene process the trench 30 is first aligned with the underlying metal line 24, and then the via 29 is aligned with the trench 30 or the metal line 24. A misalignment of the trench 30 with the metal line 24 will impact the alignment or connectivity of the via 29. If the via 29 is also misaligned with respect to the trench 30, the error is compounded. Misaligned interconnect features can result in increase current leakage, via contact resistance, and via chain resistance which all lead to yield loss.
Accordingly, the preference is to first align the via with the underlying metal line and etch it, which is done in the PVF-2LHM dual damascene process as shown in FIGS. 9 through 12. A via 39 feature is patterned in the photoresist layer 31 and then etched into the second mask film 32B of dual mask layer 32. The photoresist layer 31 is stripped and replaced with a fresh photoresist layer 46. A trench 30 feature is then patterned in the fresh photoresist layer 46. A via 39 is first etched through the first mask film 32A of mask layer 32 to a predetermine depth of trench dielectric 33 using an etch chemistry that is selective to the first mask film 32A. The trench 30 feature in the photoresist 46 is now etched into the second mask film 32B of mask layer 32. Then the via 39 is etched through the via dielectric layer 34 to the insulative barrier layer 37 as shown in FIG. 11. With respect to FIG. 12, the trench 30 is then etched through the trench dielectric layer 33 in accordance with the feature previously patterned in the photoresist layer and etched in the second mask film 32B of the mask layer 32. In a separate etching procedure, the etch stop layer 38 within the trench 30 and the barrier insulative layer 37, within the via 39, are selectively etched. The via 39 then connects an underlying conductive line 36 to a conductive line formed in the trench 30.
Misalignment in the PVF-2LHM dual damascene process can result in a reduced width of the via. With respect to FIG. 13, a semiconductor device is shown having a via 41 etched to predetermined depth of a mask layer 40 having a first mask film 40A and a second mask film 40B. A photoresist layer 42 is deposited over the mask layer 40, and a trench feature 43 is shown patterned in the photoresist layer 42 through the second mask film 40B. As represented by the dashed lines in FIG. 13, the trench feature 43 is misaligned with respect to the partially etched via 41 in the mask layer 40. When the via 41 is subsequently etched through the photoresist 42 and the dielectric material, the via 41 dimension is not fully etched in the dielectric material. The dashed line in FIG. 14, represents the originally patterned dimension of the via 41. However, as the original dimension of the via 41 did not fall within the trench feature 43 patterned in the new photoresist layer 42, the entire dimension of the via 41 cannot be etched through the dielectric material. Accordingly, the via size has been reduced. The trench 45 is then etched in the dielectric material and displaced to a side of the conductive line 44 as a result of the misalignment. The reduction in the via size which may lead to increase in via contact and chain resistances and poor device reliability and yield.